STANFORD UNIVERSITY
                     Stanford, California 94305


COMPUTER SCIENCE DEPARTMENT                    Telephone 415-321-2300
                                                       extension 4202
                          February 22, 1973


Mr. Phil Rafield
Vice President - Marketing
Digital Computer Controls, Inc.
12 Industrial Road
Fairfield, New Jersey 07006

Dear Mr. Rafield:


This letter follows up on our telephone conversation of a week  or so

ago.


A group in the  Stanford Artificial Intelligence Laboratory  has been

designing a new processor over  the past two and one-half  years.  In

informal  communications  with us  and  in a  letter  to  our sponsor

(Advanced Research Projects Agency) about a year and a half ago, your

organization expressed interest in possible commercial rights  to the

machine.  This letter summarizes the current situation.


The design of the new processor, internally called "Super Foonly", is

essentially complete.  It is  a 36 bit microprgrammed  machine which,

with suitable microcode, can run  PDP-10 code about 10 times  as fast

as  a KA-10  processor, or  about 4  times as  fast as  a  KI-10.  It

achieves this speed through the use of S-series TTL logic and  a 2000

word cache memory.
Mr. Phil Rafield                                               Page 2


Other features include  a memory map  that includes the  functions of

the BBN  and KI-10  maps, and  a "console  computer".  There  will be

almost  no  lights  or  switches  on  the  console.   Instead,  these

functions will be performed by the console computer, which will  be a

mini with display and keyboard.


The console computer will be able to examine and change  the contents

of any  register in the  big machine and  control the clock  as well.

Thus, it  can simulate  all the  display and  control functions  of a

console  and  can  also  perform  much  more  sophisticated debugging

functions.


In  support  of this  work,  we  have developed  a  number  of design

automation  programs  that run  on  displays attached  to  our PDP-10

timesharing  system.  All  logic  drawings and  printed  circuit card

designs  have  been  created  interactively  and  are  represented by

computer files.   These files are  automatically checked  for certain

kinds of consistency and are used to produce PC artwork and wirelists

directly.


The processor contains about 9000 DIPS.  Currently, all  logic design

is complete (214 drawings) and paper debugging is underway.  20 of 24

PC cards are completely designed as are 36 of 44 wirewrap  cards.  We

have  fabricated  prototype  PC  and  wirewrap  boards  and completed

engineering tests on them.
Mr. Phil Rafield                                               Page 3


Our  sponsor, ARPA,  has underwritten  the design  costs, but  is not

willing to pay for the hardware costs.  We are interested  in finding

an  organization  that  would  be willing  to  buy  the  parts  for a

prototype,  which  we  would keep,  in  exchange  for  design rights.

Toward this end, we  are opening discussions with  several industrial

groups.


The cost of parts and fabrication services for the prototype  will be

about $195,000.  It would be somewhat less with volume discounts, but

we are not in a position to obtain these for ourselves.


If you would like to examine the design more closely, I  suggest that

someone from your organization come here and receive a  briefing from

our staff.  The drawings are available for inspection.


Sincerely,



Lester D. Earnest
Executive Officer
Stanford Artificial Intelligence Laboratory