Diagnostic Functions (Read)

FR	Bit	Signal Name

100	3.7	PI1 ON 1
100	3.6	PI1 ON 2
100	3.5	PI1 ON 3
100	3.4	PI1 ON 4
100	3.3	PI1 ON 5
100	3.2	PI1 ON 6
100	3.1	PI1 ON 7
100	2.9	VMA HELD OR PC 01
100	2.8	VMA HELD OR PC 02
100	2.7	VMA HELD OR PC 03
100	2.6	VMA HELD OR PC 04
100	2.5	VMA HELD OR PC 05
100	2.4	VMA HELD OR PC 06
100	2.3	CTL SPEC/SCM ALT
100	2.2	- CTL SPEC/SAVE FLAGS
100	2.1	CTL ARL SEL 2
100	1.9	- CTL ARR LOAD A
100	1.8	- CTL AR 00-09 LOAD
100	1.6	CLK EBUS CLK
100	1.5	CLK SBUS CLK
100	1.3	CLK BURST CNT=0
100	1.2	CLK BURST 128
100	1.1	CLK BURST 64

101	3.7	PI1 GEN 1
101	3.6	PI1 GEN 2
101	3.5	PI1 GEN 3
101	3.4	PI1 GEN 4
101	3.3	PI1 GEN 5
101	3.2	PI1 GEN 6
101	3.1	PI1 GEN 7
101	2.9	VMA HELD OR PC 07
101	2.8	VMA HELD OR PC 08
101	2.7	VMA HELD OR PC 09
101	2.6	VMA HELD OR PC 10
101	2.5	VMA HELD OR PC 11
101	2.4	VMA HELD OR PC 12
101	2.3	CTL SPEC/CLR FPD
101	2.2	- CTL SPEC MTR CTL
101	2.1	CTL ARL SEL 1
101	1.9	- CTL ARR LOAD B
101	1.8	- CTL AR 09-17 LOAD
101	1.6	CLK BURST 32
101	1.5	CLK BURST 16
101	1.4	CLK BURST 08
101	1.3	CLK BURST 04
101	1.2	CLK BURST 02
101	1.1	CLK BURST 01

102	3.7	EBUS CS05 E
102	3.6	EBUS CS06 E
102	3.5	EBUS DEMAND E
102	3.4	EBUS CS00 E
102	3.3	EBUS CS01 E
102	3.2	EBUS CS02 E
102	3.1	EBUS CS03 E
102	2.9	MCL VMA READ
102	2.8	MCL MEM/ARL IND
102	2.7	MCL PAGE TEST PRIVATE
102	2.6	MCL XR PREVIOUS
102	2.5	MCL VMA_AD
102	2.4	ARMM 12
102	2.3	CTL SPEC/GEN CRY18
102	2.2	CTL COND/AR_EXP
102	2.1	CTL ARR SEL 2
102	1.9	CTL MQM SEL 2
102	1.8	CTL ARX LOAD
102	1.6	CLK ERROR STOP
102	1.5	- CLK GO
102	1.4	CLK EBOX REQ
102	1.3	CLK SYNC
102	1.2	- CLK PAGE FAIL EN
102	1.1	CLK FORCE 1777

103	3.7	PI2 TIMER DONE
103	3.6	PI5 EBUS PI GRANT
103	3.5	PI2 STATE HOLD
103	3.4	EBUS CS04 E
103	3.3	PI2 HONOR INTERNAL
103	3.2	PI2 READY
103	3.1	PI5 EBUS REQ
103	2.9	MCL VMA PAUSE
103	2.8	- MCL REQ EN
103	2.7	MCL VMA UPT
103	2.6	- MCL PREV COND
103	2.5	MCL VMA INC
103	2.4	MCL PREV SEC TO ARMM
103	2.3	CTL SPEC/SECTION HOLD
103	2.2	- CTL DISP RET
103	2.1	CTL ARR SEL 1
103	1.9	CTL MQM SEL 1
103	1.8	CTL ARL SEL 4
103	1.6	CLK DRAM PAR ERR
103	1.5	- CLK BURST
103	1.4	CLK MB XFER
103	1.3	- CLK EBOX CLK
103	1.2	CLK INSTR 1777
103	1.1	CLK 1777 EN

104	2.9	MCL VMA WRITE
104	2.8	MCL VMA USER
104	2.7	MCL PAGE UEBR REF
104	2.6	- MCL VMAX EN
104	2.5	- MCL LOAD VMA CONTEXT
104	2.4	- MCL EBOX CACHE
104	2.3	CTL SPEC/FLAG CTL
104	2.2	- CTL LOAD PC
104	2.1	CTL ARXL SEL 2
104	1.9	CTL MQ SEL 2
104	1.8	CTL AR 00-11 CLR
104	1.6	CLK CRAM PAR ERR
104	1.5	- CLK EBOX SS
104	1.4	CLK SOURCE SEL 2
104	1.3	CLK EBOX SOURCE
104	1.2	- CLK FM PAR CHECK
104	1.1	CLK MBOX CYCLE DIS

105	2.9	MCL LOAD AR
105	2.8	MCL VMA PUBLIC
105	2.7	MCL PAGE ADDRESS COND
105	2.6	MCL VMAX SEL 2
105	2.5	MCL 23 BIT EA
105	2.4	- MCL EBOX MAY BE PAGED
105	2.3	CTL SPEC/SP MEM CYCLE
105	2.2	CTL ADX CRY 36
105	2.1	CTL ARXL SEL 1
105	1.9	CTL MQ SEL 1
105	1.8	CTL AR 12-17 CLR
105	1.6	CLK FM PAR ERR
105	1.5	SH AR PAR ODD
105	1.4	CLK SOURCE SEL 1
105	1.3	CLK EBOX CRM DIS
105	1.2	- CLK CRAM PAR CHECK
105	1.1	- CLK MBOX RESP SIM

106	2.9	MCL LOAD ARX
106	2.8	- MCL VMA PREVIOUS
106	2.7	MCL PAGE ILL ENTRY
106	2.6	MCL VMAX SEL 1
106	2.5	MCL 18 BIT EA
106	2.4	MCL REG FUNC
106	2.3	CTL AD LONG
106	2.2	CTL ADX CRY 36 A
106	2.1	CTL ARXR SEL 2
106	1.9	CTL MQM EN
106	1.8	CTL ARR CLR
106	1.6	CLK FS ERROR
106	1.5	SH ARX PAR ODD
106	1.4	CLK RATE SEL 2
106	1.3	CLK EBOX EDP DIS
106	1.2	- CLK DRAM PAR CHECK
106	1.1	- CLK AR/ARX PAR CHECK

107	2.9	- MCL STORE AR
107	2.8	- MCL VMA EXTENDED
107	2.7	MCL EA TYPE 10
107	2.6	MCL EA TYPE 09
107	2.5	MCL MBOX CYC REQ
107	2.4	- MCL EBOX MAP
107	2.3	- CTL INH CRY 18
107	2.2	DIAG MEM RESET
107	2.1	CTL ARXR SEL 1
107	1.9	- DIAG LOAD EBUS REG
107	1.8	- CTL SPEC CALL
107	1.6	- CLK ERROR
107	1.5	CLK PAGE FAIL
107	1.4	CLK RATE SEL 1
107	1.3	CLK EBOX CTL DIS
107	1.2	- CLK FS CHECK
107	1.1	- CLK ERR STOP EN

110	4.8	APR SWEEP BUSY EN
110	4.3	APR SBUS ERR IN
110	4.2	APR NXM ERR IN
110	4.1	APR I/O PF ERR IN
110	3.9	APR MB PAR ERR IN
110	3.8	APR C DIR P ERR IN
110	3.7	APR S ADR P ERR IN
110	3.6	APR PWR FAIL IN
110	3.5	APR SWEEP DONE IN
110	3.4	APR APR INTERRUPT
110	3.3	PI3 APR PIA 04
110	3.2	PI3 APR PIA 02
110	3.1	PI3 APR PIA 01
110	RH	MTR TIME

111	4.3	APR SBUS ERR IN
111	4.2	APR CURRENT BLOCK 2
111	4.1	APR CURRENT BLOCK 1
111	3.9	APR PREV BLOCK 4
111	3.8	APR PREV BLOCK 2
111	3.7	APR PREV BLOCK 1
111	3.6	APR CWSX
111	3.5	APR PREV SEC 13
111	3.4	APR PREV SEC 14
111	3.3	APR PREV SEC 15
111	3.2	APR PREV SEC 16
111	3.1	APR PREV SEC 17
111	RH	MTR PERF COUNT

112	4.3	APR SBUS ERR EN IN
112	4.2	APR NXM ERR EN IN
112	4.1	APR I/O PF ERR EN IN
112	3.9	APR MB PAR ERR EN IN
112	3.8	APR C DIR P ERR EN IN
112	3.7	APR S ADR P ERR EN IN
112	3.6	APR PWR FAIL EN IN
112	3.5	APR SWEEP DONE EN IN
112	RH	MTR EBOX COUNT

113	3.9	APR FETCH COMP
113	3.8	APR READ COMP
113	3.7	APR WRITE COMP
113	3.6	APR USER COMP
113	RH	MTR CACHE COUNT

114	4.2	APR MBOX CTL 03
114	4.1	APR FM BLOCK 4
114	3.9	APR FM BLOCK 2
114	3.8	APR FM BLOCK 1
114	3.7	APR FM ADR 10
114	3.6	APR FM ADR 4
114	3.5	APR FM ADR 2
114	3.4	APR FM ADR 1
114	3.3	APR F02 EN
114	3.2	APR FM 36
114	3.1	APR FM ODD PARITY
114	RH	MTR INTERVAL

115	4.2	APR MBOX CTL 06
115	4.1	- APR SET PAGE FAIL
115	3.9	APR EBUS RETURN
115	3.8	APR EBOX DISABLE CS
115	3.7	- APR WR BAD ADR PAR
115	3.6	APR EBOX CCA
115	3.5	APR EBOX ERA
115	3.4	APR EBOX SBUS DIAG
115	3.3	- MCL MEM/REG FUNC
115	3.2	- APR EBOX LOAD REG
115	3.1	- APR EBOX READ REG
115	2.6	MTR INTERVAL ON
115	2.5	MTR INTERVAL DONE
115	2.4	MTR INTERVAL OVRFLO
115	2.3-1.1	MTR PERIOD

116	4.2	APR WR PT SEL 0
116	4.1	- APR PT DIR WR
116	3.9	- APR EBUS REQ
116	3.8	APR EBUS F01 E
116	3.7	APR ANY EBOX ERR FLG
116	3.6	APR EBOX UBR
116	3.5	APR EN REFILL RAM WR
116	2.6	MTR PI ACCT EN
116	2.5	MTR EXEC ACCT EN
116	2.4	MTR ACCT ON
116	2.2	MTR TIME ON
116	1.3-1.1	PI3 MTR PIA

117	4.2	APR WR PT SEL 1
117	4.1	- APR PT WR
117	3.9	APR EBUS DEMAND
117	3.8	APR EBOX SEND F02
117	3.7	- CON FM WRITE PAR
117	3.6	APR EBOX EBR
117	3.5	APR EBOX SPARE
117	2.7	MTR VECTOR REQ
117	2.6	MTR INCR SEL 2
117	2.5	MTR INCR SEL 1

120		AR

121		BR

122		MQ

123		FM

124		BRX

125		ARX

126		ADX

127		AD

130	4.7	SCD TRAP REQ 2
130	4.6	SCD TRAP CYC 2
130	4.5	SCD TRAP CYC 1
130	4.4	SCD TRAP REQ 1
130	4.3	SCD FPD
130	4.2	SC 05
130	4.1	SC 06
130	3.9	SC 07
130	3.8	SC 08
130	3.7	SC 09
130	3.6	IR NORM 08
130	3.5	IR NORM 09
130	3.4	IR NORM 10
130	3.3	DR ADR 00 A
130	3.2	DR ADR 01 A
130	3.1	DR ADR 02 A
130	2.9	CON WR EVEN PAR ADR
130	2.8	CON WR EVEN PAR DATA
130	2.7	CON WR EVEN PAR DIR

131	4.7	SCD OV
131	4.6	SCD CRY0
131	4.5	SCD CRY1
131	4.4	- AD CRY 01
131	4.3	SCD DIV CHK
131	4.2	SC 00
131	4.1	SC 01
131	3.9	SC 02
131	3.8	SC 03
131	3.7	SC 04
131	3.6	DR ADR 03 A
131	3.5	DR ADR 04 A
131	3.4	DR ADR 05 A
131	3.3	DR ADR 06 A
131	3.2	DR ADR 07 A
131	3.1	DR ADR 08
131	2.9	CON CACHE LOOK EN
131	2.8	CON CACHE LOAD EN
131	2.6	- CON KI10 PAGING MODE
131	2.5	CON TRAP EN

132	4.7	VMA HELD OR PC 00
132	4.6	SCD FOV
132	4.5	SCD FXU
132	4.4	- AD OVERFLOW 00
132	4.3	- AD CRY -02
132	4.2	FE 05
132	4.1	FE 06
132	3.9	FE 07
132	3.8	FE 08
132	3.7	FE 09
132	3.6	IR EN I/O, JRST
132	3.5	IR EN AC
132	3.4	IR AC 09
132	3.3	IR AC 10
132	3.2	IR AC 11
132	3.1	IR AC 12
132	2.9	- CON COND EN 00-07
132	2.8	- CON COND/SEL VMA
132	2.7	- CON COND/MBOX CTL
132	2.5	- CON LOAD IR
132	2.4	CON AR LOADED
132	2.3	CON PI CYCLE

133	4.7	SCD PCP
133	4.6	SCD LOAD FLAGS A
133	4.5	- SCAD=0
133	4.4	CON CLR PRIVATE INSTR
133	4.3	SCD NICOND 10
133	4.2	FE 00
133	4.1	FE 01
133	3.9	FE 02
133	3.8	FE 03
133	3.7	FE 04
133	3.6	DRAM A 00
133	3.5	DRAM A 01
133	3.4	DRAM A 02
133	3.3	DRAM B 00
133	3.2	DRAM B 01
133	3.1	DRAM B 02
133	2.9	- CON SKIP EN 40-47
133	2.8	CON COND/VMA_#
133	2.7	CON EBUS REL
133	2.6	- CON PC+1 INH  [- ?]
133	2.5	CON COND INSTR ABORT
133	2.4	- CON ARX LOADED
133	2.3	- CON MEM CYCLE

134	4.7	- SCD USER A
134	4.6	SCD LEAVE USER
134	4.5	- CON PI CYCLE A
134	4.4	- SCD USER EN
134	4.3	SCD PUBLIC PAGE
134	4.2	SC SIGN
134	3.6	IR TEST SATISFIED
134	3.5	- IR JRST 0,
134	3.4	DRAM J 01
134	3.3	DRAM J 02
134	3.2	DRAM J 03
134	3.1	DRAM J 04
134	2.9	- CON SKIP EN 50-57
134	2.8	CON COND/LOAD VMA HELD
134	2.7	CON SR 00
134	2.6	COND NICOND TRAP EN
134	2.5	CON LOAD ACCESS COND
134	2.4	CON UCODE STATE 01
134	2.3	- CON FM WRITE PAR

135	4.7	- SCD PUBLIC EN
135	4.6	SCD PUBLIC A
135	4.5	SCD KERNEL MODE
135	4.4	- SCD PRIVATE INSTR
135	4.3	- SCD PRIVATE INSTR EN
135	4.2	FE SIGN
135	3.6	DRAM PAR
135	3.5	DRAM ODD PARITY
135	3.4	DRAM J 07
135	3.3	DRAM J 08
135	3.2	DRAM J 09
135	3.1	DRAM J 10
135	2.9	CON DELAY REQ
135	2.8	- CON LOAD SPEC INSTR
135	2.7	CON SR 01
135	2.6	CON NICOND 07
135	2.5	- CON INSTR GO
135	2.4	CON UCODE STATE 03
135	2.3	- CON MBOX WAIT

136	4.7	SCD KERNEL OR USER IOT
136	4.6	SCD TRAP MIX 32
136	4.5	SCD TRAP MIX 33
136	4.4	SCD USER IOT A
136	4.3	- SCD USER IOT EN
136	4.2	SC > 36
136	3.6	- AD=0
136	3.5	IR I/O LEGAL
136	3.4	- CTL INH CRY
136	3.3	CTL SPEC/GEN CRY 18
136	3.2	GEN CRY 36
136	3.1	AD CRY -02 A
136	2.9	CON AR 36
136	2.8	- CON VMA SEL 2
136	2.7	CON SR 02
136	2.6	CON NICOND 08
136	2.5	CON LOAD DRAM
136	2.4	CON UCODE STATE 05
136	2.3	- CON FM XFER

137	4.7	SCD ADR BRK INH
137	4.6	SCD TRAP MIX 34
137	4.5	SCD TRAP MIX 35
137	4.4	SCD ADR BRK CYC
137	4.3	SCD ADR BRK PREVENT
137	4.2	- SCD TRAP CLEAR
137	3.6	AD CRY 12
137	3.5	AD CRY 18
137	3.4	AD CRY 24
137	3.3	AD CRY 36
137	3.2	ADX CRY 12
137	3.1	ADX CRY 24
137	2.9	CON ARX 36
137	2.8	- CON VMA SEL 1
137	2.7	CON SR 03
137	2.6	CON NICOND 09
137	2.5	CON COND ADR 10
137	2.4	CON UCODE STATE 07
137	2.3	- CON PI DISMISS

140	4.9	- DISP EN 00-07
140	4.8	- DISP EN 00-03
140	4.7	- DISP EN 30-37
140	4.6	DISP 02 A
140	4.5	DISP 03 A
140	4.4	DISP 04 A

141	4.9	CRA DISP PARITY
141	4.8	CRA DISP 00
141	4.7	CRA DISP 01
141	4.6	CRA DISP 02
141	4.5	CRA DISP 03
141	4.4	CRA DISP 04

142	4.9	SBR RET 05
142	4.8	SBR RET 06
142	4.7	SBR RET 07
142	4.6	SBR RET 08
142	4.5	SBR RET 09
142	4.4	SBR RET 10

143	4.8	SBR RET 00
143	4.7	SBR RET 01
143	4.6	SBR RET 02
143	4.5	SBR RET 03
143	4.4	SBR RET 04

144	4.9	CR ADR 05 F
144	4.8	CR ADR 06 F
144	4.7	CR ADR 07 F
144	4.6	CR ADR 08 F
144	4.5	CR ADR 09 F
144	4.4	CR ADR 10 F

145	4.8	CR ADR 00 F
145	4.7	CR ADR 01 F
145	4.6	CR ADR 02 F
145	4.5	CR ADR 03 F
145	4.4	CR ADR 04 F

146	4.9	CRA LOC 05
146	4.8	CRA LOC 06
146	4.7	CRA LOC 07
146	4.6	CRA LOC 08
146	4.5	CRA LOC 09
146	4.4	CRA LOC 10

147	4.8	CRA LOC 00
147	4.7	CRA LOC 01
147	4.6	CRA LOC 02
147	4.5	CRA LOC 03
147	4.4	CRA LOC 04

150	3.5	PC 15
150	3.3	ADR BRK 15
150	3.1	PC 19
150	2.8	ADR BRK 19
150	2.6	PC 23
150	2.4	ADR BRK 23
150	2.2	PC 27
150	1.9	ADR BRK 27
150	1.7	PC 31
150	1.5	ADR BRK 31
150	1.3	PC 35
150	1.1	ADR BRK 35

151	3.5	PC 14
151	3.3	ADR BRK 14
151	3.1	PC 18
151	2.8	ADR BRK 18
151	2.6	PC 22
151	2.4	ADR BRK 22
151	2.2	PC 26
151	1.9	ADR BRK 26
151	1.7	PC 30
151	1.5	ADR BRK 30
151	1.3	PC 34
151	1.1	ADR BRK 34

152	3.5	PC 13
152	3.3	ADR BRK 13
152	3.1	PC 17
152	2.8	ADR BRK 17
152	2.6	PC 21
152	2.4	ADR BRK 21
152	2.2	PC 25
152	1.9	ADR BRK 25
152	1.7	PC 29
152	1.5	ADR BRK 29
152	1.3	PC 33
152	1.1	ADR BRK 33

153	3.5	VMA 18-31=0
153	3.1	PC 16
153	2.8	ADR BRK 16
153	2.6	PC 20
153	2.4	ADR BRK 20
153	2.2	PC 24
153	1.9	ADR BRK 24
153	1.7	PC 28
153	1.5	ADR BRK 28
153	1.3	PC 32
153	1.1	ADR BRK 32

154	3.5	VMA HELD 15
154	3.3	VMA 15 A
154	3.1	VMA HELD 19
154	2.8	VMA 19 A
154	2.6	VMA HELD 23
154	2.4	VMA 23 A
154	2.2	VMA HELD 27
154	1.9	VMA 27 A
154	1.7	VMA HELD 31
154	1.5	VMA 31 A
154	1.3	VMA HELD 35
154	1.1	VMA 35 A

155	3.5	VMA HELD 14
155	3.3	VMA 14 A
155	3.1	VMA HELD 18
155	2.8	VMA 18 A
155	2.6	VMA HELD 22
155	2.4	VMA 22 A
155	2.2	VMA HELD 26
155	1.9	VMA 26 A
155	1.7	VMA HELD 30
155	1.5	VMA 30 A
155	1.3	VMA HELD 34
155	1.1	VMA 34 A

156	3.5	VMA HELD 13
156	3.3	VMA 13 A
156	3.1	VMA HELD 17
156	2.8	VMA 17 A
156	2.6	VMA HELD 21
156	2.4	VMA 21 A
156	2.2	VMA HELD 25
156	1.9	VMA 25 A
156	1.7	VMA HELD 29
156	1.5	VMA 29 A
156	1.3	VMA HELD 33
156	1.1	VMA 33 A

157	3.5	VMA AC REF
157	3.3	VMA MATCH 13-35
157	3.1	VMA HELD 16
157	2.8	VMA 16 A
157	2.6	VMA HELD 20
157	2.4	VMA 20 A
157	2.2	VMA HELD 24
157	1.9	VMA 24 A
157	1.7	VMA HELD 28
157	1.5	VMA 28 A
157	1.3	VMA HELD 32
157	1.1	VMA 32 A

160	3.3	CORE BUST
160	3.2	- CHAN PAR ERR
160	3.1	SH AR PAR ODD A
160	2.9	MB PAR BIT IN
160	2.8	- CSH EN CSH DATA
160	2.7	MB IN SEL 1
160	2.6	NXM ACKN
160	2.5	CHAN CORE BUSY
160	2.4	- NXM ANT
160	2.3	- NXM T6,7
160	2.2	- CHAN NXM ERR
160	2.1	PAG MB 18-35 PAR
160	1.9	FORCE VALID MATCH 0
160	1.8	FORCE VALID MATCH 1
160	1.7	FORCE VALID MATCH 2
160	1.6	FORCE VALID MATCH 3
160	1.5	WRITE OK
160	1.4	CSH ADR WR PULSE
160	1.3	- CSH DATA CLR DONE IN

161	3.3	- MBOX ADR PAR ERR
161	3.2	CBUS PAR LEFT TE
161	3.1	MEM PAR IN
161	2.9	CSH PAR BIT
161	2.8	- MEM TO C DIAG EN
161	2.7	MB IN SEL 2
161	2.6	- MBZ1 RD-PSE-WR REF
161	2.5	- MBOX NXM ERR
161	2.4	- CHAN MEM REF
161	2.3	- MBOX SBUS ERR
161	2.2	- NXM DATA VAL
161	2.1	CSH PAR BIT A
161	1.9	- CSH DATA CLR T1
161	1.8	- CSH DATA CLR T2
161	1.7	- CSH DATA CLR T3
161	1.6	CSH SEL LRU
161	1.5	CSH VAL WR PULSE
161	1.4	CSH WR WR PULSE
161	1.3	RQ HOLD FF

162	3.3	- CHAN ADR PAR ERR
162	3.2	CBUS PAR RIGHT TE
162	3.1	CSH PAR BIT IN
162	2.9	N.C.
162	2.8	- CHAN READ
162	2.7	MB IN SEL 4
162	2.6	MEM BUST
162	2.5	- HOLD ERA
162	2.4	NXM T2
162	2.3	- MBOX MB PAR ERR
162	2.2	PAG MB 00-17 PAR
162	2.1	CSH PAR BIT B
162	1.9	CACHE WR 00 A
162	1.8	CACHE WR 09 A
162	1.7	CACHE WR 18 A
162	1.6	CACHE WR 27 A
162	1.5	SBUS ADR HOLD
162	1.4	- A CHANGE COMING A
162	1.3	- ANY SBUS RQ IN

163	1.9	- B CHANGE COMING
163	1.8	CORE BUSY A
163	1.7	CSH VAL SEL ALL
163	1.6	CSH VAL WR DATA
163	1.5	CSH WR SEL ALL
163	1.4	CSH WR WR DATA
163	1.3	DATA VALID A OUT

164	1.9	DATA VALID B OUT
164	1.8	MBC INH 1ST MB REQ
164	1.7	- MEM TO C EN
164	1.6	- PHASE CHANGE COMING
164	1.5	- ACKN PULSE
164	1.4	CORE ADR 34
164	1.3	CORE ADR 35

165	1.9	CAM SEL 1
165	1.8	CAM SEL 2
165	1.7	- CORE DATA VALID -1
165	1.6	- CORE DATA VALID -2
165	1.5	- CORE DATA VALID
165	1.4	CORE RD IN PROG
165	1.3	MEM ADR PAR

166	1.9	MEM RD RQ B
166	1.8	MEM RQ 0
166	1.7	MEM RQ 1
166	1.6	MEM RQ 2
166	1.5	MEM RQ 3
166	1.4	- MEM START
166	1.3	- MEM WR RQ

167		EBUS REG

170	2.7	- CSH 0 ANY VAL
170	2.6	CSH USE IN 0
170	2.5	- PAGE REFILL COMP
170	2.4	CACHE WR IN
170	2.3	- MBOX PT DIR WR
170	2.2	- CSH WR TEST
170	2.1	ANY VAL HOLD
170	1.9	- CSH DATA CLR DONE
170	1.8	- CSH REFILL RAM WR
170	1.7	- CSH EBOX T3

171	2.7	- CSH 1 ANY VAL
171	2.6	CSH USE IN 1
171	2.5	- CHAN RD T5
171	2.4	- CSH WR DATA RDY
171	2.3	- PAGE FAIL T2
171	2.2	CSH EBOX LOAD REG
171	2.1	- CSH FILL CACHE RD
171	1.9	- CHAN WR T5
171	1.8	- MB WR RQ CLR NXT
171	1.7	- CSH EBOX T1

172	2.7	- CSH 2 ANY VAL
172	2.6	CSH USE IN 2
172	2.5	- CHAN WR CACHE
172	2.4	- CCA CYC DONE
172	2.3	- CHAN T4
172	2.2	CSH LRU 2
172	2.1	READY TO GO A
172	1.9	CSH USE HOLD
172	1.8	- CSH CCA CYC
172	1.7	- CSH EBOX REQ EN

173	2.7	- CSH 3 ANY VAL
173	2.6	CSH USE IN 3
173	2.5	- ONE WORD RD
173	2.4	- MBOX RESP
173	2.3	- RD PSE 2ND REQ EN
173	2.2	CSH LRU 1
173	2.1	- CSH T1
173	1.9	WRITEBACK T1 A
173	1.8	-CSH CCA WRITEBACK
173	1.7	- CSH EBOX T2

174	2.7	CSH DIR 0 PAR ODD
174	2.6	CSH USE IN 4
174	2.5	- E CORE RD RQ
174	2.4	- PAGE FAIL HOLD
174	2.3	- PAGE REFILL T9,13
174	2.2	- CSH 3 ANY WR
174	2.1	- CSH T0
174	1.9	CSH ADR PMA EN
174	1.8	- CSH EBOX CYC B
174	1.7	- CACHE IDLE

175	2.7	CSH DIR 1 PAR ODD
175	2.6	CSH USE ADR 2
175	2.5	- CSH EBOX RETRY REQ
175	2.4	CSH USE WR EN
175	2.3	- MB TEST PAR A IN
175	2.2	- CSH 1 ANY WR
175	2.1	- CSH T3
175	1.9	MBOX GATE VMA 27-33
175	1.8	- CSH MB CYC
175	1.7	- ONE WORD WR T0

176	2.7	CSH DIR 2 PAR ODD
176	2.6	CSH USE ADR 3
176	2.5	- CCA INVAL T4
176	2.4	- PAGE REFILL T8
176	2.3	- CSH EBOX T0
176	2.2	- CSH 2 ANY WR
176	2.1	- CSH T2
176	1.9	E CACHE WR CYC
176	1.8	- CSH E WRITEBACK
176	1.7	- PAGE REFILL T4

177	2.7	CSH DIR 3 PAR ODD
177	2.6	CSH USE ADR 4
177	2.5	- PAGE REFILL ERROR
177	2.4	- DATA DLY 1
177	2.3	PAGE FAIL DLY
177	2.2	- CSH 0 ANY WR
177	2.1	- PAGE REFILL T10
177	1.8	- RD PAUSE 2ND HALF
177	1.7	- CSH EBOX WR T4

Diagnostic Functions (Control)

FX		Operation

01		CLK FUNC START
02		CLK FUNC SINGLE STEP
03		CLK FUNC EBOX SS
04		CLK FUNC COND SS
05		CLK FUNC BURST
06		CLK FUNC CLR RESET
07		CLK FUNC SET RESET

10		CON DIAG CLR RUN
11		CON DIAG SET RUN
12		CON DIAG CONTINUE
14		CON DIAG IR STROBE
15		COND DIAG DRAM STROBE

65		clear IR EN I/O, JRST
66		clear IR EN AC
67		set IR EN I/O, JRST and IR EN AC

Diagnostic Functions (Write)

FW	Bits	Writes into

42	1.1-1.4	CLK BURST 1.1-1.4

43	1.1-1.4	CLK BURST 1.5-1.8

44	1.3-1.4	CLK SOURCE SEL 1,2
44	1.1-1.2	CLK RATE SEL 1,2

45	1.3	CLK EBOX CRM DIS
45	1.2	CLK EBOX EDP DIS
45	1.1	CLK EBOX CTL DIS

46	1.4	CLK FM PAR CHECK
46	1.3	CLK CRAM PAR CHECK
46	1.2	CLR DRAM PAR CHECK
46	1.1	CLK FS (probe) CHECK

47	1.4	CLK MBOX CYCLE DIS
47	1.3	CLK MBOX RESP SIM
47	1.2	CLK AR/ARX PAR CHECK
47	1.1	CLK ERR STOP EN

53	4.4-4.8	DISP 00-04  (CRA board)

54	 ?	CRM WRITE (60-79)

55	 ?	CRM WRITE (40-59)

56	 ?	CRM WRITE (20-39)

57	 ?	CRM WRITE (00-19)

60	 ?	DRAM LOAD X,Y EVEN

61	 ?	DRAM LOAD X,Y ODD

62	 ?	DRAM LOAD J COMMON

63	 ?	DRAM LOAD J EVEN

64	 ?	DRAM LOAD J ODD

71	1.2	- clear CSH EN CSH DATA
71	1.1	- set CSH EN CSH DATA
71		DIAG AR LOAD

73		DIAG AR LOAD

75		DIAG AR LOAD

76	2.3	DIAG MEM RESET
76	2.2	DIAG DIAG 01
76	2.1	DIAG LOAD EBUS REG
76	1.9	DIAG DIAG 03
76	1.8	DIAG DIAG 04

77		DIAG AR LOAD
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