COMMENT ⊗   VALID 00002 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00002 00002	1)	Modified PAG board 4AF30.  Added signal CON KI10 PAGING MODE L
C00005 ENDMK
C⊗;
1)	Modified PAG board 4AF30.  Added signal CON KI10 PAGING MODE L
	to pin E43(7) on PAG3 page.  This fixes the bug whereby every
	page fault looked like "no PT DIR match" in KL paging mode.
				JBR 5/10/76  0300

[I think this one is rev 9 or 9A]
2)	Modified CON board 4AF35.  Deleted CON MBOX WAIT H from pin FN1.
	Deleted wire from E62(14) to E57(9), but left terminator on E57(9).
	Added wire from E62(15) to E57(10) CON WRITE FM PAR L
	from pin FN1 to E57(9) -CLK SBR CALL L
	and from E53(4) to E57(11) -CON CLK B L.
	Modified CTL board 4AF36.  Deleted terminator on -CLK SBR CALL L.
	Added twisted pair from 4A36F1 to 4F35N1 -CLK SBR CALL L.
	This fixes the spurious FM parity error problem.
				JBR 6/5/76  1900

[NOT INSTALLED]
Rev 10 [I think]
SCD TRAP REQ n is set by CON COND INSTR ABORT and SCD TRAP CYC n.  This is
changed to CON COND INSTR ABORT and (SCD TRAP CYC n or SCD TRAP REQ 2).
If TRAP REQ n gets set but then a page fault happens on the instruction fetch
(before the NICOND dispatch can set TRAP CYC) the TRAP REQ is lost.


[NOT INSTALLED]
Rev 10A [I think]
PHYS REF causes VMAX SEL 1 and VMAX SEL 2 to force the entire VMA to be loaded.
On MCL4 (center) add an and gate with inputs from MCL SPEC MEM CYCLE and
magic numbers bit 8 with output going to E56 pin 7.  When this mod is installed,
the microcode has to be changed so that the PHYS REF appears in the same
microinstruction as VMA←AD.