perm filename INTER.S[1,VDS] blob sn#157533
filedate 1975-04-26 generic text, type C, neo UTF8
COMMENT ⊗ VALID 00002 PAGES
C REC PAGE DESCRIPTION
C00002 00002 INTERFACE NOTES- GENERAL MOTORS CONTRACT
INTERFACE NOTES- GENERAL MOTORS CONTRACT
The General Motors Order requires a total of 21 channels min. of
12 bit Analog inputs.
Seven channels of D/A - 12 bit output, with an extra bit for
each channel to command mode. This bit will set the mode in the driver
electronics which are not part of the interface.
Seven brake bits. TTL compatible. These bits can be in the form of
a seven bit word.
Interrupt logic to set flags when conversions are done, and when
arm is done, etc. as specified by GM.
For software considerations, here is a typical layout.
First address selects a channel
Second address- Data read from or write into appropriate buffer.
Put all brakes in one 7 bit word.
Put all status bits in one word
Arm done bit should provide interrupt.
Design with 32 channels of 12 bit A/D in mind.
8 channels of 12 DAC
8 brake bits
Consider effects of layout on noise,
Consider minimizing temperature drift, by airy design
Dont worry too much about 50 microsec. spec., as
if we say that the maximum slew rate of the pots is 100v/sec, or
5mv/50microsecs, then we can expect a one bit max error if conversion
does indeed take that long. In addition, there is no need for a sample and
hold, as the input signal slew rate is slow enough so that the error from
the sample time is 1 bit max. In general, we would expect no more than
about a 40 v/sec. slew, so the above numbers are conservative.
It appears then that we can do some filtering of signals with a frequency
of greater than about 100 hz.
Actually, this means that we can filter out all signals with a slope greater
than about 100 v/sec., if such a filter can be designed.